Objectives
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Invent a digital design that performs addition with minifloats - Must be designed in VHDL
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The design must be a structural implementation as opposed to a behavioural one
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The circuit must be combinational: no memory
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The structure must be clearly identified
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Each subcomponent must have a clear purpose
Methods/Features/Results
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The design is separated into three main subcomponents: the Preparator, the Adder1, and the Normalizer
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Preparator: appropriately prepares the minifloats such that mantissas can be added at the next stage
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Adder1: computes the sum of the mantissas as a basic full adder
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Normalizer: normalizes and truncates the sum from Adder1, combining it with the exponent from the start to yield the final result
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Immediately identifies edge cases, avoiding unnecessary computations when possible
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No process blocks used, avoiding the possibility of inherent memory usage